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ResearchAudio.io
OpenAI Designed a Chip in Nine Months
Built for language model inference, with the lab's own models accelerating the work.
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Nine months
design to tape-out
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End of 2026
first deployment target
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Gigawatt
target scale
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OpenAI shipped its first chip. The detail that stops you cold: it went from blank slate to manufacturing tape-out in nine months.
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On June 24, OpenAI and Broadcom unveiled Jalapeño, an accelerator built for a single job, running large language models in production. OpenAI calls it the company's first Intelligence Processor. And the team used OpenAI's own models to accelerate parts of the chip design itself.
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So this is a model company designing the silicon underneath its models. Here is what that means for anyone shipping on frontier models, and the one performance claim worth holding loosely.
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Until this, OpenAI was a models and products company that bought its accelerators. The economics of running those models (cost per token, latency, how much of a chip's theoretical throughput you actually use) were shaped by hardware built for someone else's workload.
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Jalapeño flips that. It is a blank-slate design for modern language model inference, not a general-purpose accelerator adapted from older AI workloads.
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That distinction is the entire pitch. Because OpenAI runs ChatGPT, Codex, and the API every day, it knows which kernels, memory movements, and serving patterns dominate real inference. The chip was shaped around those, with Broadcom on silicon implementation and networking, and Celestica on boards, racks, and systems.
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The stack OpenAI now controls
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Products
ChatGPT, Codex, API
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Models
frontier language models
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Serving and kernels
scheduling, deployment
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Jalapeño chip
New
language model inference
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Networking and racks
Broadcom, Celestica
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Jalapeño is the newest layer. Source: OpenAI, June 24, 2026.
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How it tries to win
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The architectural goal is simple to state and hard to do. Keep the expensive parts of the chip busy.
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Modern accelerators often stall waiting on data movement rather than compute. Jalapeño's design reduces that data movement and balances compute, memory, and networking, so realized utilization lands closer to the hardware's theoretical limits. Broadcom's Tomahawk networking silicon connects the parts at scale.
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These are not renderings. Engineering samples are already running machine learning workloads in OpenAI's lab at production target frequency and power, including GPT-5.3-Codex-Spark.
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Richard Ho, who leads OpenAI's hardware program, says early testing shows the chip executing the company's most demanding workloads close to the hardware's theoretical limits.
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Here is the part to hold loosely. OpenAI says Jalapeño will deliver performance per watt substantially better than current state-of-the-art, but it also says final performance is still being measured, with a detailed technical report due in the coming months. No benchmark numbers were released. Treat the efficiency line as a direction, not a result.
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The takeaway: the lesson is not build your own chip, it is that inference is increasingly won by co-designing silicon around your kernels and serving patterns rather than porting general-purpose accelerators. The variable that decides your serving cost is often data movement, not raw compute, which is exactly the axis Jalapeño optimizes. If you run inference infrastructure, audit where your latency is memory-movement-bound versus compute-bound this week.
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OpenAI used its own models to help design the chip that will run the next generation of those models. The stack is starting to optimize itself.
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The cast. Broadcom (silicon implementation, networking, and its Tomahawk switching) and Celestica (boards, racks, and systems) are industrializing the platform. Broadcom's Hock Tan and Charlie Kawwas handed the first chip to Sam Altman and Greg Brockman, a staging that frames this as a partnership rather than a vendor relationship.
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The scale. Initial deployment targets the end of 2026 and grows across multiple chip generations. Hock Tan framed it as gigawatt-scale data centers with Microsoft and other partners beginning in 2026.
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The loop. Better infrastructure lowers the cost of compute, which funds better models, which become better products, which fund the next chip. Vertical integration is the strategy, and the chip is the newest lever.
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The compounding part. The same models served to users helped design the hardware that will serve future models. If AI keeps shrinking chip-design cycles, the slowest layer in the stack starts moving at software speed.
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My read: the headline is not the chip, it is the nine months. ASIC programs are usually measured in years, and silicon has been the slowest, least iterable layer in AI. If a nine-month cycle holds across generations, OpenAI gets to iterate hardware at something closer to software cadence, and that compounds faster than any single chip's efficiency number.
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I would still wait for the technical report before trusting the efficiency claims, because every number here is pre-final and self-reported. But if the speed claim is real, it is the part rivals should worry about.
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If AI-assisted design keeps compressing silicon timelines, the bottleneck stops being chip design and becomes fab capacity and power. So which one breaks first for the labs racing toward gigawatt scale, the foundries or the grid? Hit reply with where you would bet.
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Inference is where AI reaches people, and OpenAI decided it wants that layer down to the transistor.
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Up next: when the Jalapeño technical report lands, I will run the performance-per-watt math against today's accelerators and translate utilization near theoretical peak into what it does to a serving bill.
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ResearchAudio.io
Source: OpenAI and Broadcom, June 24, 2026
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